Currently, the scientific group has completed the sub-activity of the project "Decomposition: development of methods and algorithms". Decomposition problems are formulated and possible solutions are found and decomposition tools are developed.

It was found that the current approach to decomposition is for circuits with simple logic elements (AND-NOT, OR-NOT), to avoid competition, double-track representation is used (variable and its inversion are represented by two separate signals), as a result of which it was concluded that the costs are very high. CMOS logic reduces complexity. Another approach is based on the use of threshold functions (Zero Convention Logic-NCL). NCL is built using 27 library elements that can implement any function with four or fewer inputs. Because dual-track representation is provided, single-track functions with more than two inputs cannot be used in an NCL environment; the feasibility of the functions depends on the number of literals in the double-track representation.

Features of the reconfigurable environment architecture function:

1) functional blocks (browser tables) that are able to implement any function with the given browser table inputs;

2) the delay from each input to output is the same;

3) wires between browsers with unknown and sometimes large delays;

4) internal feedback.

Therefore, the methods previously used in design based on simple elements should be reviewed. Although each individual browser table does not contain competitions (browser table delays are balanced), an important problem remains the implementation of the overall scheme without competitions. Due to the large delays in the wires, a model with unlimited delays is provided, i. delay insensitive model.

Decomposition tools were developed according to the criteria: area and speed. A comparison with existing tools has been made. The methods developed by us give the best results to test the effectiveness of the methods, decomposition and realization of real equipment in XILINX environment.

The research will be implemented in the ERDF Operational Program “Growth and Employment” 1.1.1. Specific support objective “To increase the research and innovation capacity of Latvian scientific institutions and the ability to attract external funding by investing in human resources and infrastructure” 1.1.1.1. within the framework of the measure “Practical Orientation Research”. The project will be implemented for 36 months, until February 29, 2020. Project “Asynchronous Logic Circuits: Methods and Software Tools for Designing in a Configurable Environment”, No. 1.1.1.1/16/A/234, the funding is EUR 287 891.90.

For more detailed information: infovirac@venta.lv